MIPS（Microprocessor without Interlocked Pipeline Stages）是一种广泛应用于计算机体系结构课程和嵌入式系统开发中的指令集架构。本文将提供一张详细的表格，展示 MIPS 指令集的一览表，帮助读者更好地理解每条指令的格式及其使用方法。

助记符 指令格式 使用样例
Bit # 31..26 25..21 20..16 15..11 10..6 5..0
R型指令 op rs rt rd shamt func
add 000000 rs rt rd 0 100000 add $t1, $t2, $t3
addu 000000 rs rt rd 0 100001 addu $t1, $t2, $t3
sub 000000 rs rt rd 0 100010 sub $t1, $t2, $t3
subu 000000 rs rt rd 0 100011 subu $t1, $t2, $t3
and 000000 rs rt rd 0 100100 and $t1, $t2, $t3
or 000000 rs rt rd 0 100101 or $t1, $t2, $t3
xor 000000 rs rt rd 0 100110 xor $t1, $t2, $t3
nor 000000 rs rt rd 0 100111 nor $t1, $t2, $t3
slt 000000 rs rt rd 0 101010 slt $t1, $t2, $t3
sltu 000000 rs rt rd 0 101011 sltu $t1, $t2, $t3
sll 000000 00000 rt rd shamt 000000 sll $t1, $t2, 10
srl 000000 00000 rt rd shamt 000010 srl $t1, $t2, 10
sra 000000 00000 rt rd shamt 000011 sra $t1, $t2, 10
sllv 000000 rs rt rd 0 000100 sllv $t1, $t2, $t3
srlv 000000 rs rt rd 0 000110 srlv $t1, $t2, $t3
srav 000000 rs rt rd 0 000111 srav $t1, $t2, $t3
jr 000000 rs 0 0 0 001000 jr $t31
Bit # 31..26 25..21 20..16 15..0
I型指令 op rs rt immediate
addi 001000 rs rt immediate(-~+) addi $t1, $t2, 100
addiu 001001 rs rt immediate(-~+) addiu $t1, $t2, 100
andi 001100 rs rt immediate(0~+) andi $t1, $t2, 10
ori 001101 rs rt immediate(0~+) ori $t1, $t2, 10
xori 001110 rs rt immediate(0~+) xori $t1, $t2, 10
lw 100011 rs rt immediate(-~+) lw $t1, 10($t2)
sw 101011 rs rt immediate(-~+) sw $t1, 10($t2)
beq 000100 rs rt immediate(-~+) beq $t1, $t2, 10
bne 000101 rs rt immediate(-~+) bne $t1, $t2, 10
slti 001010 rs rt immediate(-~+) slti $t1, $t2, 10
sltiu 001011 rs rt immediate(-~+) sltiu $t1, $t2, 10
lui 001111 00000 rt immediate(-~+) lui $t1, 10
Bit # 31..26 25..0
J型指令 op index
j 000010 address j 10000
j 000011 address jal 10000